Analog IC Design Engineer | Apple | Santa Clara Valley, CA 95014

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  • United States, Santa Clara Valley, CA 95014 View on Map
  • Post Date : November 19, 2020
  • Apply Before : December 19, 2020
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Job Description

Summary

Posted: Nov 17, 2020
Role Number:200207711
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking IC Designer. As a member of our multifaceted group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Architect, Design and Productize Analog ICs passionate about ADC/DAC.
Key Qualifications
  • Do you have a proven track record of taking chips to production in the following areas?
  • Deep knowledge of ADC/DAC architectures and knowing which are suitable for given applications
  • Deep knowledge of band-gaps, bias, op-amps, switched-cap circuits, LDOs, feedback and compensation techniques
  • Validated expertise in the following areas:
  • Significant knowledge of low noise design techniques
  • Significant knowledge of high precision techniques in presence of device mismatch Experience in C / Matlab / Verilog modeling
  • Strong device physics knowledge as it applies to analog IC designs
  • Validated working experience in using spectrum analyzers, oscilloscopes, signal generators, etc. to validate analog designs
  • Extensive experience working with production test engineers to firm up test plans and design for testability details
Description
In this role, the key responsibilities are the following: Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures. Transistor-level feasibility studies for various blocks in ADC/DAC. Crafting blocks and documenting design towards formal design reviews. Drive mask design to implement layout view of designs. Top-level simulations to validate top-level integration. Defining production/bench-level test-plans. Taking lab measurements to validate analog designs. Driving/reviewing yield/lab test results to drive bug fixes. Design for ESD compliance.
Education & Experience
Masters Degree with 2+ years in related area of expertise or PhD with 1year of relevant experience

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